1. Field of the Invention
This invention relates generally to integrated circuits comprising power MOSFETs in parallel with Schottky rectifiers. More particularly, this invention relates to a novel and improved structure and improved process of fabricating an integrated trench MOSFET and Schottky rectifier with trench contact structure upon a single substrate, which structure has improved performance with low specific on-resistance for Trench MOSFET and low Vf and reverse leakage current Ir for Trench Schottky rectifier, as well as low fabricating cost.
2. The Prior Arts
The Shottky barrier rectifiers have been used in DC-DC converters. In parallel with the parasitic PN body diode, the Schottky barrier rectifier acts as clamping diode to prevent the body diode from turning on for the reason of higher speed and efficiency, so the recent interests have been focus on the technology to integrate the MOSFET and the Schottky barrier rectifier on a single substrate. In U.S. Pat. Nos. 6,351,018, 6,987,305 and 6,593,620, methods of forming the Schottky diode on the same substrate with MOSFET are disclosed.
To integrate the MOSFET device and the Schottky barrier rectifier upon a single substrate, the Schottky structures used in U.S. Pat. Nos. 6,351,018 and 6,987,305 are designed to share the same trench gate with trench MOSFET. And one of the structures is shown in FIG. 1. An integrated trench MOSFET-Schottky diode structure is fabricated on a substrate 202 of a first doping type, into which a plurality of trenches 200 are etched. A thin layer of insulator 204 lines the sidewalls of the trenches 200, and after which the trenches 200 are filled with conductive material 206 to act as gate material. Then the well region of a second doping type is formed by diffusion between trenches except those where Schottky diode will be formed (trenches 200-3 and 200-4, as shown). After the P-well formation, source regions 212 are diffused at the surface of the substrate, followed by the formation of P+ body region 214 inside each P-well region. In order to distinguish the conductive layers playing different roles, 216 is marked to figure the connecting layer to source region 212, while 218 figures the anode of Schottky diode 210 as illustrated. And metal layer 220 is deposited to short the source region 212 and anode of Schottky diode 210.
Another integrating method is introduced in U.S. Pat. No. 6,593,620 of which trench gate of the Schottky structure is shorted with anode or source metal of the trench MOSFET, as shown in FIG. 2. A combination structure has DMOS transistor devices within DMOS transistor region 220 and has Schottky barrier rectifier devices within rectifier region 222. The entire structure includes, an N+ substrate 200 on which is grown a lightly n-doped epitaxial layer 202, which serves as the drain for the DMOS transistor devices and cathode region for the rectifier devices. Conductive layer 218 is deposited on the rear side of the substrate to act as a common drain contact for the DMOS transistor devices and as a common cathode electrode for the rectifier devices. Inside the epitaxial layer 202, body regions 204 of a second doping type is formed for the DMOS transistor devices, and N+ source regions 212 are also provided. Conductive layer 216 deposited on the front side of the substrate acts as a common source contact for the DMOS transistor devices, shoring the sources with one another, and at the same time, acts as anode electrode for the rectifier devices. Trench regions lined with oxide layers 206 and filled with polysilicon 210 are provided, and polysilicon 210 is shorted to the conductive layer 216 for the rectifier devices. Layer of 214 illustrated is BPSG layer used to insulate the polysilicon 210 from conductive layer 216 for the DMOS transistor devices. It should be noticed that, the Schottky barrier rectifier devices and the DMOS transistor devices in this patent have separated trench gates in contrast to the structure mentioned above.
Both structures in the prior arts introduced can achieve the integration of MOSFET devices and Schottky barrier rectifier devices on a single substrate, but there are still some constrains.
Conventional technologies to form both the Schottky barrier rectifier and trench MOSFET, as described above, are mainly planar contact. First of all, the planar contact occupies a large area, almost one time of MOSFET. As the size of devices is developed to be smaller and smaller, this structure is obviously should replaced by another configuration which will meet the need for size requirement. On the other hand, this planar structure will lead to a device shrinkage limitation since the contacts occupy large area, resulting in high specific on-resistance according to the length dependence of resistance.
Another disadvantage of the structures mentioned in prior arts is that, during the fabricating process, additional P+ mask or contact mask for opening of Schottky rectifier anode contact is required, and therefore need additional fabrication cost.
Accordingly, it would be desirable to provide an integrated trench MOSFET-Schottky barrier rectifier structure having lower on-resistance, lower fabricating cost, and, at the same time, having smaller device area.